Devices with different electrical gate dielectric thicknesses but with substantially similar physical configurations

ABSTRACT

An integrated circuit is disclosed having one or more devices having substantially similar physical gate electric thicknesses but different electrical gate electric thicknesses for accommodating various operation needs. One or more devices are manufactured with a same mask set using multiple doping processes to generate substantially similar physical gate dielectric thicknesses, but with different electrical gate dielectric thicknesses. The device undergoing multiple doping processes have different dopant concentrations, thereby providing different electrical characteristics such as the threshold voltages.

RELATED APPLICATION

This application is a continuation of co-pending application Ser. No.10/886,215 filed Jul. 6, 2004, the contents of which are hereinincorporated by reference as if set forth in their entirety.

BACKGROUND

The present invention generally relates to integrated circuits (IC), andmore particularly to logic and memory ICs that utilize a multi-stagedoping methodology to electrically adjust characteristics of ametal-oxide-semiconductor field effect transistor (MOSFET) and forreducing the size of the same.

As MOSFETs continuously downscale, the thermal budget, source/drainjunction depth and dopant concentration are reduced for alleviatingshort channel effects. However, there is a limit to this trend ofreduction. If the limit is exceeded, the lower poly gate doping profilecan change, which may induce an undesirable depletion region between thegate electrode and the gate dielectric layer. If the gate dopantconcentration does not saturate enough, it will increase the electricalgate dielectric thickness and degrade the MOSFET saturation current. Theelectrical gate dielectric thickness is the equivalent thickness of thegate dielectric layer under certain electrical conditions. Two MOSFETswith the same physical gate dielectric thickness may have differentelectrical gate dielectric thickness. For example, those two MOSFETsoperating under different electrical conditions, e.g., with differentgate dopant concentrations, can have significantly unmatched electricalgate dielectric thickness. In general, one of the MOSFETs may have a“thinner” electrical gate dielectric thickness than the other if it hasa greater gate dopant concentration. As such, an insufficiently dopedgate electrode usually results in an undesirably thick electrical gatedielectric thickness.

Conventionally, only a single-stage doping is performed for the gatestructures of logic devices and memory cells in fabrication of an IC,such as SRAM and DRAM. For example, in an SRAM cell design, a pass gatedevice usually requires a narrower channel width and a longer channellength than a pull-down device, in order to obtain a high β ratio andstatic noise margin (SNM). However, such design will cause an inversenarrow width effect and decrease the β ratio in a low voltage operation.The long channel length design particularly causes the size of thememory cell to increase. An optimal design for an SRAM circuit shouldhave a pass gate device with a higher threshold voltage and lowersaturation current when compared to a pull-down device. As such, theelectrical characteristics of the pass gate device and the pull-downdevice should be different.

A DRAM cell often includes a pass gate device coupled with a capacitor.In a DRAM cell design, the pass gate device leakage and capacitor gateleakage are the ones of major concerns. A lower gate leakage andsub-threshold leakage are desirable for a better data retention,reliability, and standby leakage current specification. In order toachieve these objectives, a thicker gate dielectric layer is needed forthe pass gate device than other peripheral logic devices. This disparatethickness of gate dielectric layers complicates the fabrication process.

Desirable in the art of logic and memory devices fabrication are newMOSFETs with electrically adjusted gate structures that will result inminimal cell size while still meeting or exceeding the currentelectrical performance parameters.

SUMMARY

In view of the foregoing, an integrated circuit is disclosed having oneor more devices having substantially similar physical gate dielectricthicknesses but different electrical gate dielectric thicknesses foraccommodating various operation needs. One or more devices aremanufactured with a same mask set using multiple doping processes togenerate substantially similar physical gate dielectric thicknesses, butwith different electrical gate dielectric thicknesses. The deviceundergoing multiple doping processes have different dopantconcentrations, thereby providing different electrical characteristicssuch as the threshold voltages.

The construction and method of operation of the invention, however,together with additional objects and advantages thereof will be bestunderstood from the following description of specific embodiments whenread in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a physical construction of a conventional MOSFET.

FIG. 2 illustrates physical constructions of two NMOS devices, whereinone device uses a one-stage doping gate structure and the other uses atwo-stage doping gate structure in accordance with one embodiment of thepresent invention.

FIG. 3 illustrates physical constructions of two PMOS devices, whereinone device uses a one-stage doping gate structure and the other uses atwo-stage doping gate structure in accordance with one embodiment of thepresent invention.

FIG. 4 presents a schematic of a typical SRAM cell using the proposedgate structure according to one embodiment of the present invention.

FIG. 5 presents a schematic of a typical DRAM cell using the proposedgate structure according to one embodiment of the present invention.

DESCRIPTION

FIG. 1 illustrates the physical construction of a conventional N-typeMOSFET 100. The MOSFET is constructed on a P substrate with n+ dopedareas as the source and drain electrodes on either side of thesubstrate. The distance 102 between the n+ doped areas is often known asthe channel length. The source and drain electrodes are identical andcan be interchanged, depending on the application of voltages. Devicesprocessed with advanced technologies may have a channel length less than1 micron, and such devices may be referred to as sub-micron devices ornano-devices. In this example, the electron current flow will begenerated by the electrode connected to Vss (source), and travel throughthe conducting channel 104 as determined by the gate voltage (Vgs) tothe electrode connected to Vds (drain). If the gate voltage is zero, noelectron current will flow from the source to the drain. The gateterminal is composed of a doped polysilicon electrode 110 connected toVgs, which is separated from the conducting channel 104 by a gatedielectric layer 106. This separation forms a parasitic capacitancebetween the gate electrode 110 and the conducting channel 104. Acapacitance is also formed between the conducting channel 104 and the Psubstrate due to a depletion region 108 that is formed during the ICfabrication.

FIG. 2 illustrates an integrated circuit module having at least twodevices whose gate structures are electrically adjusted to achievevarious electric characteristics, according to one embodiment of thepresent invention. The NMOS transistors 202 and 206 are used as anexample for explaining the embodiment. The NMOS transistor 202 utilizesa single-stage gate doping method to form a lightly doped first gateelectrode 204 atop a first gate dielectric layer 205. The NMOStransistor 206 utilizes the proposed two-stage gate doping method toform a heavily doped second gate electrode 208 atop a second gatedielectric layer 209.

The construction of NMOS transistors 202 and 206 are identical exceptfor their gate dopant concentrations. While the physical thicknesses ofthe first and second gate dielectric layers 205 and 209 areapproximately the same, the gate dopant concentrations for the gateelectrodes 204 and 208 are substantially different. The first gateelectrode 204 has a first gate dopant concentration that isapproximately 50% lower than a second gate dopant concentration of thesecond gate electrode 208. Typically, the physical gate dielectricthicknesses of the first and second gate dielectric layers 205 and 209are less than about 20 Angstroms. However, the electrical performance ofthe first and second dielectric layers 205 and 209 are substantiallydifferent that results in at least an equivalent difference of a 2Angstroms in the physical thickness due to the different dopantconcentrations. In some cases, it can be more than 5 Angstroms indifference. It is understood that for the purpose of this invention, theelectrical gate dielectric thickness is measured in terms of physicalthickness.

In an IC that uses only the one-stage doping method, all MOSFETs withinthat IC will have the same gate dopant concentrations. In an IC thatuses the proposed two-stage doping method, its MOSFETs would havedifferent gate dopant concentrations as determined by operation needsfor optimal IC device performance and reduced device size.

The two-stage gate doping methodology utilizes basically the same masksand same process steps as the conventional SRAM/DRAM. However, thetwo-stage gate doping utilizes an additional gate doping process forincreasing the dopant concentration on selected devices. For example, agate dielectric layer is first formed on a conducting channel betweenthe source and drain by a chemical vapor deposition (CVD) process. Apolysilicon layer is then formed atop the gate dielectric layer by aprocess, such as CVD and sputtering. This polysilicon layer is dopedwith N-type impurities for improving its conductivity. Thereafter, asecond-stage doping is performed on selected devices. The second-stagedoping results in a higher dopant concentration in the gate structuresthan those doped in the one-stage process. In NMOS transistors as shownin FIG. 2, an N-type impurity, such as As, P31 and Sb, is used in thefirst-stage doping and the second stage doping. After the two-stagedoping, subsequent fabrication processes are performed to complete boththe one-stage and the two-stage doped transistors.

FIG. 3 presents a cross-sectional view of two identical PMOS transistors302 and 306 except for their gate doping concentrations. A PMOStransistor 302 utilizes the conventional one-stage gate doping method toform a lightly doped first gate electrode 304, while a PMOS transistor306 utilizes the proposed two-stage gate doping method to form a heavilydoped second gate electrode 308. In PMOS transistors as shown in FIG. 3,a P-type impurity, such as B11, BF2, and In, is used in the first-stagedoping and the second stage doping. It is noteworthy that theconstructions of both transistors are identical except for their gatedopant concentrations. Like NMOS transistors 202 and 206 in FIG. 2, thephysical thicknesses of the first gate dielectric layer 305 and thesecond gate dielectric layer 309 are less than about 20 Angstroms.However, the performance of the first and second gate dielectric layers305 and 309 are so different that results in at least an equivalent2-Angstrom performance difference in terms of their electrical gatedielectric thicknesses.

As an another embodiment of this invention, more than two stage dopingsmay be implemented to create multiple gate dopant concentrations indevices, such as memory cells and logic devices. This would electricallyadjust device characteristics to accommodate various operation needs.After the first and second gate doping processes are completed, morerounds of gate doping processes are performed on selected devices withinan IC in order to form even more heavily doped gate structures.

This invention has an advantage of creating two devices with twodifferent electrical gate dielectric thicknesses without altering thephysical gate dielectric thickness. Thus, no additional mask is requiredto form a dielectric layer with different thicknesses in various areas.The lightly doped gate electrode has a higher threshold voltage, whilethe heavily doped gate electrode has a lower threshold voltage. Byselecting devices for the different dopant concentrations, they mayaccommodate various operational needs. For example, a memory cell, suchas an SRAM cell and a DRAM cell, often have devices requiring variousthreshold voltages.

FIG. 4 presents an example that this invention is applied in asix-transistor SRAM cell 400 that incorporates both the one-stage dopeddevices and the proposed two-stage doped devices. The SRAM cell 400contains a cross-coupled inverter 402 and two pass gate devices 404 and406. It is understood that there are additional peripheral logic deviceswithin the IC (not shown in this figure) that interface with, andcontrol over the pass gate devices 404 and 406 for data read/writefunctions of the SRAM cell 400. The cross-coupled inverter 402 iscomprised of two inverter circuits. One inverter includes a pull-up PMOStransistor 408, and pull-down NMOS transistor 410, while the secondinverter includes a pull-up PMOS transistor 412 and pull-down NMOStransistor 414. Unlike a DRAM cell, the SRAM cell 400 does not have tobe periodically refreshed. The SRAM cell 400 retains data bits in itsmemory by the states of the two cross-coupled inverter 402 as long aspower is applied to it. The NMOS pass gate devices 404 and 406 areturned on by the appropriate word line WL to allow the differentialvoltages on the bit lines BL and BLB to be read from or written to theSRAM cell 400, as determined by the peripheral logic devices thatcontrol the bit lines BL and BLB.

The present two-stage doped gate structure can be implemented on theSRAM cell 400 by applying the two-stage gate doping process on selecteddevices, while all other devices would utilize the one-stage gate dopingprocess. In this embodiment, the pass gate devices 404, 406 and Pull-upPMOS transistors 408, 412 will remain as one-stage, lightly dopeddevices due to their low gate leakage requirements. The Pull-down NMOStransistors 410, 414, and other peripheral logic devices (not shown inthis figure) such as decoder circuits, NAND devices, NOR devices,inverter devices, selector circuits, sense amplifier circuits, etc., aswell as other high performance devices (not shown in this figure) suchas decoder circuits, NAND devices, NOR devices, inverter devices, wouldincorporate the two-stage doping process for reducing their gate channellength, and therefore, the device physical size. Typically thethicknesses of the gate dielectric layers for the pass gate devices 404,406, Pull-up PMOS transistors 408, 412, Pull-down NMOS transistors 410,414 and peripheral logic devices are less than 15 Angstroms. Thephysical gate dielectric thickness of all those devices aresubstantially the same, while the gate dopant concentration of thePull-down NMOS transistors 410, 414 are substantially higher than thePull-up PMOS transistors 408, 412 and the pass gate devices 404, 406. Inaddition, the gate dopant concentration of the peripheral logicaldevices and high performance devices are substantially greater than thePull-down NMOS transistors 410, 414. The higher gate dopantconcentration is about 50% greater than the lower gate dopantconcentration. This results in the Pull-down NMOS transistors-410, 414having electrical gate dielectric thicknesses substantially thinner thanthe pull-up PMOS transistors 408, 412 and the pass gate device 404, 406.The peripheral logic devices and high performance devices haveelectrical gate dielectric thicknesses substantially thinner than thepull-down NMOS transistors 410, 414.

The two-stage gate doping process would reduce the electrical gatedielectric thickness of these heavily doped devices, while leaving thepass gate devices 404, 406 and pull-up PMOS transistors 408 and 412 tobe manufactured using the one-stage doping method on these devices. Theadvantage of using the two-stage gate doping process on the pull-downNMOS transistors and peripheral logic devices would result in a higher Pratio, a higher SNM at lower operational voltages, a higher thresholdvoltage, and most importantly, a smaller device physical size. Theseadvantages are gained without additional masks or costs that would haveincurred if a gate dielectric layer with various thicknesses areimplemented.

FIG. 5 presents a typical DRAM memory circuit 416 as another example ofthis invention which incorporates both the conventional one-stage andthe proposed two-stage gate doping method within an IC. The simplifiedDRAM memory circuit 416 includes a pass gate device 418, a bit storagecapacitor 420, and the peripheral logic devices (not shown). Thecapacitor 420 acts as the memory storage device by maintaining a charge(data value “1”) or no charge (data value “0”). The capacitor istypically a MOSFET device whose source and drain are electricallyconnected together. The gate dielectric layer between the gate and thesource/drain connection acts as the capacitance. The pass gate device418 allows for the read, write, or refresh of the capacitor 420 ascontrolled by the word line WL and the status of the bit line BL. InDRAM devices, it is essential that the pass gate device 418 and thecapacitor 420 have low leakage to maximize the data retention time.Therefore, both the pass gate 418 and capacitor 420 should utilize theone-stage lightly doped gate doping method. However, the peripherallogic devices (not shown) and the high performance devices (not shown)within the IC can utilize the two-stage method to reduce their physicalsize and still meet their electrical performance requirements. Therelationship of the gate dopant concentration and electrical gatedielectric thickness are similar to that as discussed above. As the SRAMcircuit 400, the embodiment of this invention, which utilizes amultiple-stage gate doping method for making DRAM devices, furtherreduces the device physical size without compromising on theperformance.

It is noted that the present invention does not require any additionalmask for implementing the additional doping process to form differentgate dopant concentrations. In other words,multiple-dopant-concentration gate structures are created amongdifferent transistors on their interface between Si and gate dielectriclayers. As such, the process effectively creates two or more classes ofeffective core gate dielectric thickness with no additional mask needed.As any additional masks can cost significantly for the manufacturing,the present invention provides an economical solution for fabrication.In addition, since the same mask set is used, the only additionalprocess added for altering the electrical characteristics is theadditional doping process (es), there is no additional cost for addingthe extra doping steps to the regular manufacturing process flow.Furthermore, due to the different electrical thicknesses available byusing different doping concentrations, pass gate device leakage orcapacitor leakages are reduced. The beta ratio and static noise marginat lower operating voltage are improved.

The above invention provides many different embodiments or examples forimplementing different features of the invention. Specific examples ofcomponents and processes are described to help clarify the invention.These are, of course, merely examples and are not intended to limit theinvention from that described in the claims.

Although illustrative embodiments of the invention have been shown anddescribed, other modifications, changes, and substitutions are intendedin the foregoing invention. Accordingly, it is appropriate that theappended claims be construed broadly and in a manner consistent with thescope of the invention, as set forth in the following claims.

1. A memory circuit having one or more devices having substantiallysimilar physical gate dielectric thicknesses but different electricalgate dielectric thicknesses, the memory circuit comprising: a firstdevice comprising: a first gate dielectric layer, having a firstphysical gate dielectric thickness, formed on a substrate; a first gateelectrode, having a first dopant concentration, formed atop the firstgate dielectric layer; a second device comprising: a second gatedielectric layer, having a second physical gate dielectric thickness,formed on the substrate; a second gate electrode, having a second dopantconcentration, formed atop the second gate dielectric layer, wherein thefirst physical gate dielectric thickness is substantially the same asthe second physical gate dielectric thickness, and the first dopantconcentration is made substantially greater than the second dopantconcentration by at least one predetermined doping process after thefirst device has undergone a prior doping process with the second deviceto cause the first physical gate dielectric thickness to be thinner thanthe second physical gate dielectric thickness by no less than twoAngstroms.
 2. The memory circuit of claim 1 wherein the second physicalgate dielectric thickness is at least 5 Angstroms greater than the firstphysical gate dielectric thickness.
 3. The memory circuit of claim 1wherein the first and second device have sub-micron channel lengths. 4.The memory circuit of claim 1 wherein the first physical gate dielectricthickness and the second physical gate dielectric thickness are lessthan about 20 Angstroms.
 5. The memory circuit of claim 1 wherein thefirst dopant concentration is at least 50% greater than the seconddopant concentration.
 6. The memory circuit of claim 1 wherein the firstgate electrode and the second gate electrode are doped with one or moreN-type impurities.
 7. The memory circuit of claim 1 wherein the firstgate electrode and the second gate electrode are doped with one or moreP-type impurities.
 8. A DRAM circuit module comprising: a capacitancedevice for data storage; a pass gate device for selectively enabling thecapacitance device to be electrically charged, wherein the pass gatedevice comprises: a first gate dielectric layer, having a first physicalgate dielectric thickness, formed on a substrate; a first gateelectrode, having a first dopant concentration, formed atop the firstgate dielectric layer; a peripheral logical device for operating withthe pass gate device, wherein the peripheral logical device comprises: asecond gate dielectric layer, having a second physical gate dielectricthickness, formed on the substrate; a second gate electrode, having asecond dopant concentration, formed atop the second gate dielectriclayer, wherein the first physical gate dielectric thickness issubstantially the same as the second physical gate dielectric thickness,and the second dopant concentration is made substantially greater thanthe first dopant concentration by at least one predetermined dopingprocess after the pass gate device has undergone a prior doping processwith the peripheral device.
 9. The DRAM circuit module of claim 8wherein the pass gate device has a first electrical gate dielectricthickness substantially greater than a second electrical gate dielectricthickness of the peripheral logic device.
 10. The DRAM circuit module ofclaim 8 wherein the first physical gate dielectric thickness and thesecond physical gate dielectric thickness are less than 20 Angstroms.11. The DRAM circuit module of claim 10 wherein the second dopantconcentration is at least 50% greater than the first dopantconcentration.
 12. (canceled)
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